1. Field of the Invention
The present invention relates generally to an oscillator, and more particularly, to a low phase-noise oscillator.
2. Description of the Related Art
Quadrature phase clock generation finds applications in many communication systems. For RF front-ends, quadrature phase is required for image rejection receivers and for down-converting RF/IF signals to baseband. For high speed clock and data recovery (CDR) systems, quadrature phase is required for half-rate phase detection, phase-interpolation, and frequency detection.
One of three approaches can be adopted to generate quadrature phase: First, a quadrature VCO (QVCO) can be used. Second, a divide-by-two circuit can generate quadrature phases if a VCO runs at twice the required frequency. Third, a polyphase filter can be employed to generate the 90° phase shift at the cost of increased power dissipation and sensitivity to component mismatches. For RF front-ends, direct-conversion or zero-IF is currently the dominating architecture for integrated solutions. A direct conversion transceiver will often avoid QVCO to prevent LO pulling. However, two emerging trends in RF design make QVCO a preferred alternative to conventional approaches. For software-defined radio transceivers as described in R. Bagheri, et al., “An 800 MHz-6 GHz software-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, pp. 2860-2876, December 2006, which is incorporated herein by reference, both the receive down-conversion and transmit up-conversion harmonic-rejection mixers, as described in J. A. Weldon, et al., “A 1.75 GHz highly-integrated narrowband CMOS transmitter with harmonic-rejection mixers,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, February 2001, pp. 160-161, which is incorporated herein by reference, require eight clock phases, which can be derived from QVCO output using a divide-by-2 circuit. For an ultra-wideband (UWB) transmitter, QVCO can drive a direct conversion transmitter because LO pulling is not an issue with UWB signaling.
A number of quadrature LC oscillators have been reported as described in the following: P. Andreani and X. Wang, “On the phase-noise and phase-error performances of multiphase LC CMOS VCOs,” IEEE J. Solid-State Circuits, vol. 39, pp. 1883-1893, November 2004; M. Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1018-1024, July 2001; T. P. Liu, “A 6.5 GHz monolithic CMOS voltage-controlled oscillator,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, February 1999, pp. 404-405; J. E. Rogers and J. R. Long, “A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, February 2002, pp. 254-255; J. Lee and B. Razavi, “A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 38, pp. 2181-2190, December 2003; S. L. J. Gierkink, et al., “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE J. Solid-State Circuits, vol. 38, pp. 1148-1154, July 2003; and A. Ravi, et al., “An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18-μm digital CMOS process,” in Dig. IEEE Symp. VLSI Circuits, June 2003, pp. 141-144, all of which are incorporated herein by reference. Coupled oscillators, as described in aforementioned references P. Andreani and X. Wang, “On the phase-noise and phase-error performances of multiphase LC CMOS VCOs,” M. Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” and T. P. Liu, “A 6.5 GHz monolithic CMOS voltage-controlled oscillator,” operate away from the resonance frequency of the tanks so as to create the required phase shift, thus providing a trade-off between reliability of oscillation and the phase noise as described in T. P. Liu, “A 6.5 GHz monolithic CMOS voltage-controlled oscillator.” In addition, they have two stable states at two different oscillation frequencies. An oscillator can lock into either one of the two stable states during power-up, resulting in unpredictable oscillation frequencies and I/Q ±90° phase ambiguity.
The multi-phase oscillator, as described in J. E. Rogers and J. R. Long, “A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS,” drives transmission lines by gain stages loaded by resistors, resulting in additional energy loss in each cycle and thus, higher phase noise. A multi-phase circular LC delay line oscillator as described in J. Lee and B. Razavi, “A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology,” requires relatively small total capacitance, which would result in higher available noise power (proportional to kT/C). Superharmonic-coupled QVCO as described in S. L. J. Gierkink, et al., “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling” and A. Ravi, et al., “An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18-μm digital CMOS process,” are free from the performance/reliability trade-offs and bimodal oscillation problems associated with coupled QVCO. A transformer is employed in S. L. J. Gierkink, et al., “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling” to couple the tail nodes of two differential VCOs together. A. Ravi, et al., “An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18-μm digital CMOS process” cross-couples the current-control transistors at tail nodes. Neither approach, however, is particularly effective in reducing phase noise.
The application of the noise filtering technique as described in E. Hegazi, J. Rael, and A. Abidi, “The Designer's Guide to High-Purity Oscillators”, New York: Kluwer, 2005, pp. 50-57 and E. Hegazi, H. Sjöland, and A. A. Abidi, “A filtering technique to lower LC oscillation phase noise,” IEEE J. Solid-State Circuits, vol. 36, pp. 1921-1930, December 2001, both of which are incorporated by reference herein, in a differential form is briefly mentioned in S. L. J. Gierkink, et al., “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling.” The circuit is shown in FIG. 1. The capacitor 101 that is intended to sink current source noise in the noise filtering technique must be removed in order to prevent the oscillator from generating two, instead of four phases. Thus, the thermal noise produced by the current source contributes to the phase noise and causes an increase in the noise factor. In addition, the noise filtering technique imposes a need for high impedance values looking into the tail nodes at twice the oscillation frequency. As a result, a large inductance and a small capacitance value would be chosen. Such a design decision would cause two problems: First, there would be a significant amount of I/Q mismatch due to the presence of a capacitance mismatch between the two copies of differential VCOs. Capacitance mismatch is inevitable, due to variations in the manufacturing process. Second, it would limit the noise distribution between the two copies of differential VCOs, and the benefit of a 3-dB phase noise reduction by combining two copies of VCOs cannot be fully realized. Furthermore, the voltage headroom consumed by the current source will result in a lower figure-of-merit than that of the proposed method.
The proposed circuit contains no current source. According to the conventional understanding of LC-VCO, this oscillator would appear to operate in the voltage-limited region, which would have a lower figure-of-merit. This is not the case, however, because the increased current consumption will cause a higher amplitude in the tail tank waveform, causing the transistor Vgs to drop. Thus, a negative feedback mechanism works to limit the current consumption. As a result, the proposed circuit never operates in the voltage-limited region. Transistors can be sized much larger to reduce I/Q mismatch without causing a drop in its figure-of-merit as would be the case for conventional oscillators without a current source.